The invention relates to placing a computer system into a sleeping state.
The xe2x80x9cAdvanced Configuration and Power Interface Specificationxe2x80x9d (xe2x80x9cACPI Specificationxe2x80x9d), version 1.0, published in February 1998, by Intel Corporation, Microsoft Corporation, and Toshiba K.K., defines several sleeping states that allow a computer to enter one of several reduced power modes with a corresponding level of system context preservation. One of these sleeping states, the xe2x80x9cS1xe2x80x9d state, is associated with low wake-up latency and full system context preservation.
For most computers, the xe2x80x9cS1xe2x80x9d state is a xe2x80x9cstop clockxe2x80x9d state, in which the computer""s processor xe2x80x9csnoopsxe2x80x9d transactions between other computer components to maintain cache coherency, but the processor itself does not carry out transactions. A wide variety of events typically cause a computer to exit the xe2x80x9cS1xe2x80x9d sleeping state, including wake events from the computer""s real-time clock, from PCI devices such as modems and network interface cards (NICs), from USB compliant peripherals such as keyboards and multimedia components, and from the computer""s power-wake button, or front panel switch.
Some computer systems, such as those based on the Intel 32-bit (IA-32) architecture, include a simple xe2x80x9chardware handshakexe2x80x9d mechanism that supports low wake-up latency sleeping states like the xe2x80x9cS1xe2x80x9d state. This mechanism involves the assertion and deassertion of a control signal, known as the STPCLK# signal, each time a system sleep event or a recognized wake event occurs. The computer""s processor receives the STPCLK# signal directly and, in response to assertion of the signal, temporarily halts program execution.
Other computer systems, such as those based on the Intel 64-bit (IA-64) architecture, are not designed to support low wake-up latency sleeping states like the xe2x80x9cS1xe2x80x9d state. In particular, processors that implement the IA-64 architecture do not recognize the STPCLK# signal and therefore do not enter a sleeping state when the STPCLK# signal is asserted. Therefore, these systems do not comply with the xe2x80x9cPC 99 System Design Guidexe2x80x9d (xe2x80x9cPC 99xe2x80x9d), published by Intel Corporation and Microsoft Corporation in August 1998, which requires the system to support the ACPI xe2x80x9cS1xe2x80x9d sleeping state.
The systems and techniques described here allow computer manufacturers to support low wake-up latency sleeping states, such as the ACPI xe2x80x9cS1xe2x80x9d state, in computer systems not originally designed to support such states. One resulting benefit is that only minor modifications are needed to bring existing computer architectures into compliance with the PC 99 standard. For example, the Intel IA-64 architecture becomes PC 99 compliant by adding only a few hardware components and modifying the operation of system BIOS only slightly.
The invention involves a computer""s entry into or exit from a sleeping state, such as the ACPI xe2x80x9cS1xe2x80x9d state, in which program execution halts. Upon detecting a sleep or wake event, a system component generates a sleep or wake signal that instructs the computer to enter or exit the sleeping state. This sleep or wake signal is of a type to which the computer""s processor does not respond. Therefore, another system component, such as BIOS, takes steps that cause the processor to halt program execution.
Other embodiments and advantages will become apparent from the following description and from the claims.